Taking on the tough hardware challenges in nextgen embedded systems

Next-gen embedded systems face many new hardware design challenges: higher performance processors that operate at low power; faster and more sensitive interface protocols, and new methods of network connectivity, among others. Fortunately there are many solutions emerging to deal with them.

DesignCon 2015 news, analysis and events round-up

A roundup of recent news, blogs and analysis articles covering all aspects of the upcoming 2015 DesignCon at the Santa Clara Convention Center, Jan. 27-30.

Get more wiggle room in your design’s RMS Phase Jitter budget

Getting that extra RMS jitter margin gives your hardware design a little extra room to breathe when estimating what’s needed to guarantee the system’s reliability and robustness.

ABCs of signal integrity for embedded developers – Part 1: Basic SI rules and methods

ABCs of signal integrity - Part 1 explores some of the challenges of designing for signal integrity and possible solutions.

Building quality & signal integrity into PoP-based PCB design & assembly

Why designers of printed circuit boards for nextgen ICs need to be savvy about package-on-package technology.

Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1

This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter them. Part 1 " Defining Clock Jitter

Improve FPGA communications interface clock jitters with external PLLs

The problems faced in dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes and how external phase locked loops (PLLs) can be used to resolve them.

Innovative defense techniques for damping digital to RF crosstalk

Many mobile devices have multiple-input-multiple-output (MIMO) on-board antennas and present many challenges to signal integrity. Here is one approach to design that reduces noise significantly and makes comm links more immune to interference.

Pinning down the acceptable level of jitter for your embedded design

You can’t rely on chip vendor specs about jitter because each vendor specifies it differently and it varies for different applications. It’s up to you to nail down the acceptable amount of jitter your design can tolerate. 

Practical EMI troubleshooting with a mixed domain oscilloscope

How to use a mixed domain oscilloscope to test and troubleshoot high performance, wirelessly connected embedded systems designs for electromagnetic interference problems.

Signal versus power integrity in high-speed embedded design

Analysis of both signal integrity and power integrity is vital to a successful high-speed digital design. Here's some perspective on why this is so and why in embedded designs the two need not be working a cross-purposes to one another.

The basics of clock jitter in embedded system designs

With the increasing system data rates, timing jitter has become critical in system design, especially where system performance limit is determined by the system timing margin, making it important to understand the impact of timing jitter.

Avoiding embedded PCB design defects

Printed Circuit Board defects can remain latent until failure occurs, so it is important to implement disciplined practices at the original stages of an embedded hardware design through to final assembly and manufacturing. 

Educational Resources

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